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WCMA1008C1X
128K x 8 Static RAM
Features
* Voltage Range -- 4.5V-5.5V * Low active power -- Typical active current: 6 mA @ f = fmax (70 ns speed) * Low standby current * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE features * CMOS for optimum speed/power (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW) The WCMA1008C1X is available in a standard 32-pin 450-mil-wide body width SOIC and 32-pin TSOP type I.
Functional Description
The WCMA1008C1X is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable
Logic Block Diagram
Pin Configuration
Top View SOIC
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER
I/O 0 I/O 1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5
POWER DOWN
512x 256x 8 ARRAY
CE1 CE2 WE OE
COLUMN DECODER A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
I/O 6 I/O 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
TSOP I Top View (not to scale)
OE A10 CE1 I/O7 I/O I/O6 6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
April 5, 2002
WCMA1008C1X
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND ....... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage[1]..................................-0.5V to VCC +0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA
Product Portfolio
Power Dissipation Operating, Icc VCC Range Product WCMA1008C1X Min. 4.5 V Typ.[2] 5.0V Max. 5.5V Speed 70 ns 55 ns Temp. Ind'l f = fmax Typ.[2] 6 mA 7.5 mA Max. 15 mA 20 mA Typ.[2] 4 A Max. 20 A Standby (ISB2)
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 4.5V-5.5V
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Typical values are measured at VCC = 5V, TA = 25C, and are included for reference only and are not tested or guaranteed.
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WCMA1008C1X
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 WCMA1008C1X-55 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND VI VCC GND VI VCC, Output Disabled f=fMAX=1/tRC IOUT =0 mA VCC = Max., Test Conditions VCC = Min., IOH = - 1 mA VCC = Min., IOL = 2.1 mA 2.2 -0.3 -1 -1 7.5 0.1 Min. 2.4 0.4 VCC +0.3 0.8 +1 +1 20 2 2.2 -0.3 -1 -1 6 0.1 Typ.[2] Max. WCMA1008C1X-70 Min. 2.4 0.4 VCC +0.3 0.8 +1 +1 15 1 Typ.[2] Max. Units V V V V A A mA mA
Max. VCC,CE1VIH,CE2ISB2
2.5
15
15
A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 9 Unit pF pF
AC Test Loads and Waveforms
R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 5V
R1 1800 ALL INPUT PULSES 3.0V 90% R2 990 GND
3 ns
(a)
OUTPUT R2 5 pF 990 INCLUDING JIG AND SCOPE (b)
90% 10%
3 ns
10%
Equivalent to:
THEVENIN EQUIVALENT 639 1.77V OUTPUT
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
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WCMA1008C1X
Switching Characteristics[4] Over the Operating Range
55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE[7] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[5, 6] Z[6] 55 45 45 0 0 45 25 0 5 20 70 60 60 0 0 50 30 0 5 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[5] Z[5, 6] 5 20 0 55 0 70 0 20 5 25 OE HIGH to High 5 55 20 0 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 Max. Unit
CE1 LOW to Low Z, CE2 HIGH to Low Z[5] CE1 HIGH to High Z, CE2 LOW to High Z[5, 6] CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down
Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE1 LOW and CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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WCMA1008C1X
Data Retention Characteristics (Over the Operating Range)
Parameter VDR Description VCC for Data Retention VCC = VDR = 3.0V, CE1 VCC - 0.3V, CE2 < 0.3V VIN VCC - 0.3V or, VIN 0.3V 0 70 Conditions Min. 2.0 Typ.[2] Max. Unit V
ICCDR tCDR[3] tR[8]
Data Retention Current
1.5
20
A
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
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WCMA1008C1X
Switching Waveforms
Read Cycle No.1[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
DATA OUT
Notes: 8. Full Device operatin requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at Vcc(min) > 100 s. 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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WCMA1008C1X
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[7. 12, 13]
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 14 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE1 or CE2 Controlled)[7, 12, 13]
tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA
OE tSD DATA I/O DATAIN VALID tHD
Notes: 12. If CE1 goes HIGH and CE2 LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 13. Data I/O is high-impedance if OE = VIH. 14. During this period the I/Os are in the output state and input signals should not be applied.
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WCMA1008C1X
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[12]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATAI/O NOTE 14 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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WCMA1008C1X
Ordering Information
Speed (ns) 70 55 Ordering Code WCMA1008C1X-GF70 WCMA1008C1X-TF70 WCMA1008C1X-GF55 WCMA1008C1X-TF55 Package Name G32 T32 G32 T32 Package Type 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Industrial Operating Range
Package Diagrams
32-Lead (450 MIL) Molded SOIC, G32
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WCMA1008C1X
Package Diagrams (continued)
32-Lead Thin Small Outline Package T32
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WCMA1008C1X
Document Title: WCMA1008C1X, 128K x 8 Static RAM REV. ** Spec # 38-14022 ECN # 115241 Issue Date 4/24/2002 Orig. of Change MGN Description of Change New Datasheet
Page 11 of 11

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